a) Field of the Invention
The present invention relates to a disk device, and in particular to a circuit for processing servo information and a method of generating a signal representative of the position of a head for reading/writing data in an auxiliary storage of an electronic data processing device using a disk type storage medium.
b) Description of the Related Art
As personal computers have recently been improved in performance and their costs have been reduced, data storage devices, in particular magnetic disk devices, are strongly demanded to provide a large quantity of storage capacity and to reduce its cost.
For this reason, the electronic circuits for disk devices have been year by year integrated into smaller circuits while incorporating large storage capacity with increasing technology. Prior to describing the operation of the electronic circuit, current disk formats will be described.
FIGS. 1A, 1B, 1C and 1D show an example of a disk format. A disk format is mainly classified into a sector (SSCT78 in FIG. 1B) provided for controlling the position of a head on a recording medium, which records/reproduces a data, and a data sector (DSCT79) provided for storage of user data. The SSCT78 comprises an Automatic gain control gap (AGCG) 60, a Servo mask (SVMK) 61, an Index mark (IDXM) 76/Sector mark (SCTM) 77, a Cylinder address (CYL) 63, a Servo sector address (SSA) 64 and a Positioned pattern (POS) 65.
The AGCG 60 and SVMK 61 are areas provided for controlling the read gain of servo information and for detecting the leading position of SSCT78, respectively. The IDXM76/SCTM77 are areas for identifying the leading position of a track or sector. The CYL 63 and the SSA 64 are areas for storing the cylinder number (track number) and the servo sector address, respectively.
The POS65 usually stores therein four pieces of information for precisely positioning a head among cylinders (burst signals A66, B67, C68, D69) and is used for controlling the precise positioning operation (settling) and tracking (following) operation to constantly position the head on a desired cylinder.
On the other hand, the DSCTA 79 comprises an Inter sector gap (ISG) 70, PLO pattern (PLO) 71, byte sync data (BS) 72, user data (DATA) 73, and an Error correcting code (EGC) 74. The ISG 70 is an area for absorbing the variations in rotation of the disk. The PLO 71 is an area for synchronization of read data with clock. The BS 72 is an area for detecting the timing in which serial data is converted into parallel data. The DATA 73 is an area for storing the user data therein. The ECC 74 is an area for checking whether or not there is an error in the read DATA 73 and for correcting the error if any.
DSCTB 79 is the format in which SSCT 78 is inserted into DSCTA 79, fundamentally. However, PLO 71, BS 72 are repeatedly disposed. This means, while reading out, since read processing is interrupted once when passing SSCT 78, therefore, it is necessary to carry out clock synchronization and byte synchronization to activate read processing again.
Now, the configuration of a prior art circuit for controlling the present format will be described with reference to FIGS. 2 to 5.
FIG. 2 is a block diagram showing the system configuration of a disk device 1 adopting a data surface servo format. The disk device 1 comprises a disc control device 2, signal processing device 12, motor driver 14, R/W amplifier 13, R/W head 7 and data surface recording medium 15. The disk control device 2 comprises a data processing unit 3, servo control unit 4 and CPU 5. The data processing unit 3 comprises a host interface control unit 10, buffer control unit 9, drive interface unit (hereinafter referred to as “drive I/F control unit) 6 and ECC control unit 8 and may include a data buffer 11 in the data processing unit 3. FIG. 2 shows the system configuration in which the data buffer 11 is included in the data processing unit 3.
In this configuration, the data processing unit 3 is integrated into single LSI (data processing device). Each of the motor driver 14 and the signal processing device 12 is integrated into single LSI.
Now, operation of each of the above-mentioned blocks will be described by a way of reproducing operation of data in a case where the disk format shown in FIGS. 1A, 1B, 1C and 1D is adopted.
The CPU 5 calculates the address on the recording medium 15 where the data which is requested by a host computer is stored and informs the servo control unit 4 of it. The servo control unit 4 detects the CYL 63 and POS 65 via the signal processing device 12 and outputs to the motor driver 14 a control signal to cause R/W head 7 to settle on and to track the cylinder where the requested data exists. The servo control unit 4 also detects SSA 64 shown in FIG. 1B and informs the drive I/F control unit 6 of the sector address of PSCT 79 where the R/W head 7 is positioned. The motor driver 24 controls the voice coil motor (VCM) based upon the control signal and also outputs a control signal for the spindle motor.
On the other hand, the drive I/F control unit 6 determines as to whether or not the data sector address informed from the servo control unit 4 matches a desired sector. If they match, the drive I/F control unit 6 generates a read instruction signal to the signal processing device 12 for initiating reading of data. The signal which is read out by the R/W head 7 and R/W amplifier 13 is synchronized with the read data with reference to PLO 71 shown in FIG. 1C in the signal processing device 12 and is discriminated into a clock and a Non return to Zero (NRZ) data. The DATA 73 shown in the drawing is processed so that the serial data is converted into parallel data based upon BS 72 and the converted data is transferred to the drive I/F control unit 6.
The control unit 6 also transfers the parallel data to ECC control unit 8 simultaneously with the transfer to the buffer control unit 9. In the ECC control unit 9, error detection for DATA 73 is conducted based upon the read DATA 73 and ECC 74. If an error is detected, the error can be corrected. If no error is detected, the DATA 73 is transferred to the host computer 16 from the buffer control unit 9 via the data buffer 11 and the host interface control unit 10. A description of the recording operation of data will be omitted herein since the data to be recorded is transferred in a path which is substantially reverse to the reproducing operation.
The circuits which are strongly correlated with the present invention are the signal processing device 12, servo control unit 4 and the drive I/F control unit 6. Now, each of these blocks will be described.
FIG. 3 shows the configuration of the circuit of the signal processing device 12, which comprises an Automatic gain control (AGC) 17, filter 18, burst signal detector 22, pulse generator 19, clock generator 20, encoder/decoder (EN/DEC) 21 and a central processing unit interface (CPU I/F) circuit 93A. The AGC 17 is adapted to automatically control the amplitude gain of a signal (RDATA) 44 which is read from the recording medium 25 via the read/write (R/W) amplifier 13. The filter 18 eliminates the noise components in the signal. The pulse generator 19 is adapted to generate a digital signal (pulse) from the read out analog signal.
At this time, the above-mentioned SVMK 61, IDXM 76/SCTM77, CYL 63 and SSA 64 are fed to the servo control unit 4 as a read data pulse (RDP) 39. The clock generator 20 generates a clock which is synchronized with the pulse which is generated in the pulse generator 19 and outputs it to EN/DEC 21. The EN/DEC 21 encodes the NRZ data when data is written in synchronization with the sync clock and decodes the digital signal when the data is read. The EN/DEC 21 conducts conversion of parallel data into serial data during a write operation and conversion of serial data into parallel data during a read operation.
The burst signal detector 22 detects an analog burst signal Aout[0:3] (hereinafter referred to as Aout 38) corresponding to each burst area from the analog signal output from the filter 18 in accordance with an instruction of the servo control unit 4 and outputs it. The CPU I/F circuit 93A is a circuit which conducts read/write of a register disposed within each circuit and is connected to the CPU 5 via the serial I/O 92 as shown in FIG. 2.
FIG. 4 shows an exemplary configuration of a prior art servo control unit 4. A servo control sequencer 23 which is an essential part of the servo control unit 4 detects the above-mentioned SVMK 61, IDXM 76/SCTM77 from a read data pulse (RDP) which is detected in the read data pulse (RDP) detecting circuit 26 and outputs SG 35, DCHG 36 and CHA 37 as detection instruction signals for the burst signal detector 22 in the signal processing device 12 based upon these signals. The sequencer 23 generates IDXMF 58 representing that the leading position of the track was detected to a sector pulse (SCTP), generating circuit 32 (which will be described hereafter) if it detects IDXM 76.
The servo control unit 4 converts the above mentioned Aout 38 into a digital value by using an A/D converter 24 and each digital value is kept in a burst register (A, B, C, D) 25 so that it can be read by the CPU 5. A gray code converter 27 and current servo address latch 28 are provided to determine the cylinder address (CYL) 63 and the servo sector address (SSA) from the read data pulse (RDP) 39. Writing of data into these burst registers (A,B,C,D) 25 or the current servo address latch 28 is conducted in response to a Write instruction signal (BSTLT 90 or SADRLT 94) from the servo control sequencer 23.
The servo sector address (SSA) 64 is transferred to a data sector information table 31, which in turn outputs the address (DSA) 41 of the data sector 79 which follows the servo sector 78 corresponding to each SSA 64, the position of a sector pulse (SCTP) 42 representing the leading position of next data sector 79 and the leading position of the next servo sector 78.
The sector pulse (SCTP) generating circuit 32 generates an SCTP42 in the SCTP 42 generating position shown in its table 31 and also generates an index pulse (IDXP) 43 from the IDXMF 58 which is generated in the servo control sequencer 23. The data sector address generating circuit 33 outputs a data sector address (DSA) 41 shown in its table 31. A split length generating circuit 34 outputs position information (SPTL 40) for temporarily suspending data processing in a data sector 79 which is disposed just before the next servo sector 78.
The CPU I/F circuit 93B is a circuit for causing CPU 5 to access to a register in the servo control unit 4 and is connected to a CPU address/data bus 91 as shown in FIG. 2.
FIG. 5 is a block diagram showing the configuration of the drive I/F control unit 6. The drive I/F sequencer 46 controls timing of inputting and outputting of signals to and from the drive I/F control unit 6. An ID/DATA comparator 47 determines as to whether or not the DSA which is detected in the servo control unit 4 matches the DSA which is requested by the sequencer 46. If the result of comparison shows a match, a data transfer unit 49 transfers data to the buffer control unit 9 from the signal processing device 12 and vice versa on request of data read and write operations, respectively.
If the servo sector 78 is disposed in the length of the data sector 79, the processing suspending circuit 48 generates a split enable signal (SPTEN 80) in response to a processing suspension instruction signal from the SPTL 40 generated in the servo control unit 4 and SG 35 and feeds it to each circuit. The CPU I/F circuit 93C is a circuit for causing the CPU 5 to conduct an access to a register in the drive I/F control unit 6 as is similar to the servo control unit 4 and is connected to a CPU address/data bus 91 as shown in FIG. 2.
In the above-mentioned prior art disk device 1, the burst signal (Aout 38) which is read from the recording medium 15 and output from the signal processing device 12 is an analog value as is disclosed in, for example, Japanese Unexamined Patent Publication No. Sho 57-86910. Accordingly, it is necessary to convert this signal into a digital signal. This A/D conversion has heretofore been conducted by the servo contort unit 4 having an A/D converter 24 as shown in FIG. 4 or a single A/D converter.
If the A/D conversion of the burst signal is conducted in the servo control unit comprising an LSI incorporating the A/D converter 24 therein as shown in the drawing, similarly to the above-mentioned prior art, the analog signal would be processed in the servo control unit. The servo control unit is a digital (logical) circuit excepting the A/D converter 24. Operation noise will give an adverse influence to the A/D converter 24. Accordingly, the number of steps for designing the servo control unit would be increased or a countermeasure circuit would be necessary when the LSI of the servo control unit is designed in order to eliminate the problem of noise. This results in an increase in manufacturing cost. Incorporation of the A/D converter 24 makes it difficult to achieve a reduction in size, which is achieved by an improvement in the process of manufacturing the LSI. Use of a single A/D converter will increase the number of parts of the electronic circuit. This is not a good idea.
A case in which the A/D converter 24 and the burst register 25 are incorporated in the signal processing device 12 will be considered. Although the above-mentioned problem are mitigated in this case, the CPU 5 should be able to read the burst registers (A, B, C, D) 25 which are shown in FIG. 4. If the CPU serial I/O 92 shown in FIG. 2 is used at this time, it would take a longer period of time to read the burst registers so that it is not suitable for fast servo control.
If the CPU address/data bus 91 shown in FIG. 2 is used, reading of data could be conducted in a parallel manner and a terminal for connecting the CPU address/data bus 91 to the signal processing device 12 would be necessary. Accordingly, the number of terminals of the large scale integrated signal processing device 12 would be remarkably increased.
Another problem will occur in this case. The CPU 5 accesses to the burst register 25 and various registers which are disposed in the data processing unit 3. Since the values on the CPU address/data bus 91 will change to various values, digital noise will occur in the signal processing device 12. There is a risk that the A/D converter 24 of the signal processing device 12 will malfunction due to influence of the noise. In order to prevent this malfunction, the price of the device may increase due to additional circuits.
A prior art method of generating a head position signal which is another object of the present invention will now be described.
A further format of the disk device adopting the data surface servo system of the general disk device is shown in FIGS. 6A, 6B and 6C.
A track 201 comprises a servo sector 202 in which head positioning information is stored and a data sector 203 in which user's data is stored.
The servo sector 202 comprises a Servo Sync 204 for synchronizing the circuits of a servo signal, Servo Mark 205 for decoding the servo signal, Index Sector Mark 206 for determining whether the servo sector in interest is an index sector, Cylinder Address 207 which is representative of a cylinder number and is usually recorded by a gray code, Head Address 208 representative of a head number, Servo Sector Address 209 representative of the servo sector address in the track, and check code CRC 210 for detecting a read error of 208 to 209. The addresses which are denoted as 207 to 210 are generally referred to as “track number area 216”. The servo sector 202 further includes a positional signal area 217 for positioning the head, which is behind the track number area 216. The positional signal area 217 comprises Positions A to D (211 to 214) which are burst signals. A Gap 215 is provided as a gap of an interface with the data sector behind the positional signal area 217.
The data sector 203 comprises a Data Sync 220 for synchronizing the circuits of the User Data 222 which follows, Data Mark 221 representative of the timing to decode the User Data 222, ECC 223 for checking whether there is an error in the User Data 222, and Pad 224 for absorbing the delay of data occurred from HDC to the medium. A gap of interface of following data sector or servo sector is a Gap 215. Thus, a general format has been described.
Now, the manner how the storage device will conduct positioning of a head by using a servo sector will be described with reference to the diagram of FIG. 7 illustrating a method of decoding the positional signal.
A case in which the head 304 reads the servo sector 202 will be described. It is presumed that the head 304 is a dual head in which a write head 305 and a read head 306 are separately provided.
As mentioned above, the servo sector 202 includes the track number area 216 and the positional signal area 217. When the head 304 passes a track n, read head 306 reads information stored in the track number area 216. Then, the storage device will recognize the number of the track through which the head 304 passes at this time based upon this information.
The storage device detects the offset of the head 304 from the track n of interest, based upon an output signal from the real head 306 when it passes the positional signal area 217. In other words, when the head 304 passes through the positional signal area 217 (POSA–POSD), a read signal shown in FIG. 9 is detected. The storage device detects the peak value of the signal and generates Va to Vd by holding its maximum value. The microcomputer of the storage device can accept the positional information by the A/D converter accepting this voltage Va to Vd and by determining the positional signal. In the case shown in the drawing, the head can be positioned in a target track by positioning so that Va−Vb=0.
A R/W channel will be described with reference to FIG. 8.
During a data write operation, write data is fed to the R/W channel from HDC 701 together with a write request. A write system circuit 702 conducts encoding of the write data which is suitable for writing to the medium. Thereafter, the write system circuit 702 feeds the encoded data to the head 304 via a head amplifier 703. The head 304 writes this data into the medium.
During a data read operation, the head 304 reads data from the medium after completion of positioning of the head on the track of interest. The read out signal is input to the R/W channel via the head amplifier 703.
After the amplitude of the signal is kept at a constant level by a VGA 704 (Variable Gain Amplifier) which keeps the amplitude of the read out signal at a prescribed level, and the noise component is eliminated in an LPF 705 (Low Pass Filter), the signal is converted digital form by an ADC 706 (Analog to Digital Converter). Then the data is PR (Partial Response) equalized by a PR equalizer 707 and is input to a Viterbi decoder 709. Thereafter, in order to decode the signal which has been subjected to encoding suitable for recording in the medium during the write operation, the signal is passed through the decoder 15 circuit 710 for decoding the encoded data. Then, read the out data is fed to HDC 701. A PLL 711 is provided for synchronization of the read out signal.
Holding of the peak value of the above-mentioned Va to Vd (POSA to POSD) is conducted by a peak hold (PEAK HOLD) circuit 712 in accordance with the timing of an external control circuit (Charge: CHA signal). Then, the servo control circuit (note: HDC 701 incorporates this servo control circuit therein in the case of FIG. 8) accepts a peak value which is determined by peak hold (PEAK HOLD) circuit 712. This acceptance is carried out after the signal has been converted into digital form by an A/D converter. The servo control circuit conducts an operation for positioning control of the head by using the digitally accepted peak value as positional information.
Technology which is related with generation of such a positional signal is disclosed in, for example, the above-mentioned Japanese Unexamined Patent Publication No. Sho 57-86910.
In the prior art, the positional information is obtained by simply detecting a peak voltage of a positional signal as shown in a block diagram of positional signal decoding in FIG. 9. Therefore, there is a problem that if a noise component 401 is superposed on the peak of the positional signal, VI rather than V in FIG. 9 may be treated as a peak value of the positional signal.
It is necessary to extend the duration of the positional signal for detection of the peak in order to extend the time constant of the peak hold circuit for noise reduction. Accordingly, the servo sector area should be increased. This leads to an extension of the time constant, an increase in the number of parts for servo control, a reduction in storage area for data, and a reduction in format efficiency of the medium.